(1) Field of the Invention
This invention relates to ROM (Read Only Memory) manufacturing techniques, and more particularly to the formation of closely spaced self-aligned word lines for use in ROM integrated circuits.
(2) Description of the Related Art
ROM devices are well known and widely used in the computer technology. In general, a ROM device is an array of MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) arranged in columns and rows where selected MOSFETs are rendered permanently conductive, or non-conductive, depending on the type of transistor. The ability to set the conductive state of each MOSFET provides a means for storing binary information. In a ROM device, this information is maintained even when power is removed from the circuit.
A typical ROM structure is illustrated in FIGS. 1 to 3. A ROM device consists basically of a plurality of parallel, closely spaced, line regions 12, called "bit lines" formed of a heavily doped impurity in a semiconductor substrate 10 having an opposite type background impurity. An insulating layer 14 overlies the substrate 10. A plurality of parallel closely spaced conductive lines 16, called "word lines", arranged orthogonally to the line regions 12, are provided on the surface of the substrate 10 on layer 14. Suitable insulating layers 18 and 20 provide insulation for the lines 16. There is also provided a metallurgy layer (not shown) that operatively connects the line regions 12, and conductive lines 16 to suitable circuitry to address and interrogate the device array, which is well known in the art.
It can be seen that at the intersection of a word line 16 and a pair of bit lines 12, there is provided an MOSFET. The spaced line regions 12 are the source and drain, the conductive line 16 is the gate electrode, and the layer 14 is the gate insulation layer. Selected MOSFETs can be made permanently conductive by implanting, and activating by an annealing step, a region 22, of an impurity of an opposite type as lines 12, between adjacent lines 12 and beneath the conductive line 16. The regions 22 are called code implants and are placed in the substrate to encode specific binary information.
As the capacity of ROM devices has continued to increase, cell size and other critical dimensions must continually be reduced. One means of increasing the ROM capacity is to increase the density of the conductive lines in the ROM device. However, the line width and spacing between lines is limited by lithographic resolution.
Researchers in the integrated circuit field generally have used the sidewall technology to form smaller spaces than normally available through lithography for various purposes. Examples of this type of application are shown in U.S. Pat. No. 4,839,305 to J.K. Brighton, and U.S. Pat. No. 4,868,136 to A. Ravaglia.
However, in the read only memory field researchers have used two layer polysilicon structures to make more densely packed memories, such as described in Y. Naruke U.S. Pat. No. 5,002,896. While these have been successful, it is clear that a single layer, closely spaced technology would provide advantages over the two layer structures. One single layer method is disclosed by Hsue in U.S. Pat. No. 5,236,853. One advantage of the single layer structure is in the increased planarity of the surface compared to the planarity of a two layered structure. Other advantages are cost effectiveness and process simplicity. Also, characterization of the ROM can be achieved in a single code implant rather than two separate implant steps.